Today's consumer electronic and wireless markets are under heavy pressure to reduce costs, increase performance, minimize power consumption and increase security. Configurability and programmability, which are accomplished with OTP memories, are the key enablers to achieving these goals.
Electrical fuse (eFuse) technology is a one-time programmable memory that is programmed by forcing a high current density through a conductor link to completely rupture it or make its resistance significantly higher. FIG. 1 shows a conventional eFuse 101 after programming. The eFuse is typically formed from a polysilicon layer 103, over an oxide layer 105, on substrate 107, with a passivation layer 109 over the polysilicon layer. The polysilicon layer may include cobalt or nickel silicide on top, and the fuse is programmed by an electromigration mechanism, in which electron momentum pushes the silicide atoms out of the conductor link along the direction of electron flow. Debris and shards 111 remain after programming. However, CMOS technology has advanced to metal gates at 32 nanometer technology nodes and beyond. Therefore, eFuses based on polysilicon (and silicide) are no longer available. Thin metal fuses can be utilized instead, but they require a much larger programming current as a draw-back. Further, all e-fuses require an extra mask and extra process steps (such as thin-film deposition and etch) and are large in size.
An antifuse is the opposite of an eFuse. The circuit is open (i.e., high resistance) at the start and is programmed to close (or short) the circuit by applying electrical stress that creates a low resistance conductive path. In the prior art, a hard gate oxide breakdown is used as the one-time programmable non-volatile memory mechanism. FIG. 2 illustrates a conventional 2-transistor (2-T) antifuse bitcell. As shown, one transistor servers as the anti eFuse with logic poly program gate (WLP) 201 and another transistor serves as the selector transistor 203 are formed over gate oxide 205 and oxide 207 (typically thicker than 205), respectively, over substrate 209, with spacers 211 on opposite sides of each gate. N+ region 213 is formed in N-type lightly doped drain (NLDD) region 215 in the substrate between the two gates, and a bit line contact 217 is formed over another N+ region on the opposite side of selector transistor 203. The breakdown is intended by applying a high voltage on WLP 201, so that the gate oxide breakdown can occur between gate 201 and NLDD region 215. Before the breakdown, the gate oxide isolates the gate and the source like a capacitor, and after breakdown, it behaves like a resistor between the gate and the source.
However, programming a 2-T antifuse can result in the oxide breaking down in one of three areas, the transistor channel 219 (below the gate), from the gate to the NLDD region (shown at 221), and from the gate to a halo (leakage reduction) implant region (shown at 223). Oxide breakdown to the channel is the desirable mechanism, since it results in a more uniform and tighter current distribution for the programmed bit cells. Breakdown to the NLDD region produces a resistive path from the gate to the substrate and a low-threshold voltage (Vt) tail, resulting in a current spread across bit cells in the array. Breakdown to the halo implant produces a high-Vt tail and results in a second peak of cell current for programmed cells. Thus, the three regions in a 2T structure produce a multi-modal current spread for bit cells.
FIG. 3 illustrates another known antifuse, a metal gate antifuse including 1T1C bitcell. Adverting to FIG. 3, the capacitor based antifuse includes an N+ metal gate 301 formed with a thin high-k dielectric layer 303 and N+ source/drain regions 305 in Nwell 307 of substrate 309, with access transistor 311 connected to a row. When a programming voltage is applied to the gate, breakdown can occur between the gate and either the N+ region or the Nwell, and a high reading current is sensed. The main drawback of the 1T1C bitcell is that the access transistor includes a thick oxide, such that the transistor is bulky and occupies significant silicon area.
As illustrated in FIG. 4, selected wordline 401 is biased with Vread, and selected bitline 403 is biased as ground, for reading bit 405 (at the cross point of the selected wordline and bitline), and other unselected wordlines and bitlines 407 are floating. For a selected bit (at an intersection of a wordline and a bitline) at high resistance, little current will flow from the wordline to the bitline, and for the selected bit at low resistance, a large current will flow from the wordline to the bitline. Therefore, if selected bit 405 is at high resistance and unselected bits 409 have a low resistance status, a current (called a sneak current) will flow along the arrows in the picture, bypassing the selected bit. This current does not tell us information about the selected bit and would lead to misread of the bit 405.
To prevent sneak currents in a simple cross-point memory array, a select transistor is required for each bit. Since two transistors are still needed for one bit, this antifuse is area inefficient. Attempts have been made to utilize diodes for such cross-point memory arrays to prevent sneak current, as illustrated in FIG. 5. Specifically, memory element 501, including top electrode 503, bottom electrode 505, and memory layer 507 sandwiched between 503 and 505, is formed with diode 509 at each intersection of a wordline 511 and a bitline 513. However, diodes incur process complexity and/or area penalty.
A need therefore exists for methodology enabling manufacture of an area-efficient, low power, high-performance, reliable OTP memory which is compatible with CMOS system-on-chip (SOC) technology, and the resulting device.